China industry top tenMaster the core

In the history of the semiconductor industry growth depends on the process node every time caused by the decline in the cost of miniature transistors; but the next generation of chip will not be accompanied by a decline in the cost of, this would be the most serious challenge to the semiconductor industry in recent 20~30 years face.

Specifically, a new generation of 20 nm bulk high-k metal gate (bulkhigh-Kmetalgate, HKMG) CMOS process, and 16/14 nano FinFET will give rise to smaller transistor logic gates, but each of the cost will be higher than the current 28 nm bulk HKMGCMOS process. This cost problem is partly derived from the new process node, which is difficult to maintain high parameter yield (parametricyields) and low defect density (defectdensity).

The 20 nm node is difficult to achieve low leakage, because the doping uniformity (dopinguniformity), line edge roughness (lineedgeroughness) and challenged control other physical parameters, the parameters of the subtle changes in the manufacturing process are very sensitive. In addition to the demand for dual graphics (doublepatterning) 20 nm node, it also brings a higher than 28 nm per wafer cost.

16/14 nano FinFET process node and the 20 nm node using wires of the same structure, so the chip area is only 20 nm node small 8~10%; the process node is also faced with stress control, overlay (overlay), and the other with ladder structure of 3D coverage (stepcoverage), process uniformity related factors the.

Per gate cost estimation for each process node in a semiconductor

The cost will be permanent, because with 28 nm bulk CMOS process maturity, wafer depreciation cost (depreciationcost) than the initial production stage of high yield climb and decline 60~70%, so each gate cost will be 28 nm bulk HKMGCMOS process is much lower than that of FinFET, and even to the fourth quarter of 2017 is the same. And 20 nm HKMG process will also be in the 2018 or 2019 depreciation costs decline, faced with similar trends.

Block CMOS process and FinFET process per gate cost estimation

Data show that the FinFET process can be used in high performance or high density design, but used in mainstream semiconductor components is not cost-effective; therefore face semiconductor industry is not coordinated between technology and customer driven foundry industry's demand. This is not the end of the sign, when the semiconductor process to 10 nm and 7 nm micro node, will bear industry has not fully prepared for the additional wafer fabrication challenges.

Seek solutions

To reduce the cost of future semiconductor transistors and logic gate node, the industry has four main solutions:

1 using the new component structure

One of the options is depleted silicon on an insulating cover (fullydepletedsilicon-on-insulator, FDSOI), each gate can bring cost than bulk CMOS and FinFET process and low leakage.

18 using 2 inch wafer

18 inch (450mm) wafer is the main challenge, which is the choice of the process node to convert; a possible situation is 10 nm and 7 nm node. However, 18 inch wafers and ultra violet lithography is not suitable for the same process node enabled, which makes the problem more complicated.

A 18 inch wafer factory to reach 40 thousand monthly wafer production in the 7 nm node, will cost $12 billion to $14 billion, and must quickly reach the high yield in a short time, otherwise the cost of depreciation will bring substantial losses. Such a wafer plant will need to produce a wafer that can quickly reach a high yield. To overcome these challenges will require a lot of effort, but only a very small part of the global semiconductor industry has the ability to do; estimated 18 inch wafer will start production in 2020.

3 enhanced entity design and manufacturing design technology

16/14 nano FinFET complex design cost may be as high as $400 million or more, and to improve the parameters of yield may have to pay 100 million or 200 million dollars; this means that the application only very few can afford it, because the product revenue must be ten times the cost of the design. In addition, the design needs to be completed within 12 months, in order to support such as smart phones, such as the rapid change of the market cycle of terminal applications.

4 the ability to use software programming on embedded multi-core processors

Programmable architecture will be expected to expand the use, but the power consumption and the cost of the embedded FPGA core is very high, software customization requires relatively process time, due to the complex task of development and debugging. Software development tools need to be enhanced, but the speed of progress is slow.